the source code for the fractal I did recently. It contains a VGA timing
generation, a PS/2 mouse controller, a clock divider with a DCM, a
pixel calculating unit for the fractal calculation and a controller
that makes the design working.
||This is the schematic of the FPGA board. I didn't
encounter bigger problems with the design so I decided to put it
online. The design was developed using EAGLE 4.1.
diploma thesis has the title "Synthesisable IP
Cores for Irregular LDPC Code Decoding Based on Highly Flexible
Architecture Templates". There I developed two highly flexible LDPC
code decoder in generic VHDL code. With this generic VHDL code,
different supported scheduling strategies and three suboptimal
algorithms one has a powerful construction kit to compose the LDPC
decoder of choice in terms of throughput, area, communications
performance and codeword size. The templates could be used for
standards like DVB-S2, IEEE 802.16e (WiMax) and IEEE 802.11n (WiFi)
that contain LDPC codes for error correction. Also I developed an IRA
LDPC code encoder, that allows encoding like necessary for the DVB-S2
Unfortunately I am not allowed to publish my diploma thesis.
||This is the assembler code of the star field I coded on my processor made with LISA.|